Round Robin Arbiter

Shared resources like memory controllers and system buses require arbitration to ensure multiple agents can access the resource without data collision or starvation. A round-robin arbiter provides strict fairness by rotating the highest priority to the requester immediately following the last agent serviced.

The module receives a 3-bit request vector req and asserts a single bit in a 3-bit registered output vector grant corresponding to the winning requester. Priority rotates in a circular queue (0, 1, 2, 0). When a grant is issued, the priority pointer updates so the granted requester now has the lowest priority, making the next sequential requester the highest priority. If a requester drops its request before its turn, the arbiter seamlessly skips it and grants the next active requester in the sequence within the same clock cycle. If no requests are active, the grant vector is zero and the priority pointer holds its previous state.

Timing and reset rules: • Clock edge: posedge clk • Reset type: Asynchronous, active-low (negedge rst_n) • Output values on reset: grant goes to 3'b000. The internal priority state must reset such that requester 0 has the highest priority. • Priority updates: The priority pointer must update only on cycles where a grant is actively issued. • Output registration: grant is a registered output. It updates on the clock edge based on the inputs present at that edge.

Worked trace: • Cycle 1: rst_n=0 → grant=3'b000, priority goes to req 0 • Cycle 2: rst_n=1, req=3'b001 → grant=3'b001 (req 0 wins), next priority is req 1 • Cycle 3: req=3'b111 → grant=3'b010 (req 1 wins), next priority is req 2 • Cycle 4: req=3'b101 → grant=3'b100 (req 2 wins, req 1 is skipped), next priority is req 0 • Cycle 5: req=3'b000 → grant=3'b000 (no requests), priority remains req 0 • Cycle 6: req=3'b100 → grant=3'b100 (req 2 wins, req 0 and 1 are skipped), next priority is req 0 • Cycle 7: req=3'b110 → grant=3'b010 (req 1 wins), next priority is req 2 • Cycle 8: req=3'b110 → grant=3'b100 (req 2 wins), next priority is req 0 • Cycle 9: req=3'b111 → grant=3'b001 (req 0 wins), next priority is req 1 • Cycle 10: req=3'b010 → grant=3'b010 (req 1 wins), next priority is req 2

{ "signal": [
  { "name": "clk",   "wave": "p.........." },
  { "name": "rst_n", "wave": "01........." },
  { "name": "req",   "wave": "x=========.", "data": ["3'b001", "3'b111", "3'b101", "3'b000", "3'b100", "3'b110", "3'b110", "3'b111", "3'b010"] },
  {},
  { "name": "grant", "wave": "==========.", "data": ["3'b000", "3'b001", "3'b010", "3'b100", "3'b000", "3'b100", "3'b010", "3'b100", "3'b001", "3'b010"] }
], "head": { "text": "10-cycle arbitration trace showing fairness and skipped requests." } }

| Signal | Direction | Width | Description | |---------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; grant goes to 0 | | req | input | 3 | Active-high request vector | | grant | output | 3 | Active-high grant vector (one-hot or all zero); registered |

Constraints

• Clock edge is posedge clk.
• Reset is asynchronous, active-low (negedge rst_n).
• On reset, grant must be 3'b000 and the internal priority state must reset such that requester 0 has the highest priority.
• Output grant must be strictly registered (no combinational paths from req to grant).
• grant must be one-hot if any request is active, or all zeros if no requests are active.
• The priority pointer must only update when a grant is actively issued. If grant is 3'b000, the priority pointer must not change.
• When a grant is issued, the priority immediately drops to the lowest level for the winning requester, making the next sequential requester the highest priority.

Topics

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