SR NOR Latch: Memory Phase Duration Verification
An active-high SR NOR latch serves as a fundamental memory element that retains its stored state indefinitely until explicitly overwritten. The latch forces its output Q to 1 when S is 1 and R is 0, and holds its current state when both inputs are 0. Three signals are shown: S (set input), R (reset input), and Q (output, initially 0). Trace Q across all 16 time steps.
Constraints
- The output
Qresponds asynchronously and immediately to changes inSandR. - The memory state must persist without degradation as long as both inputs remain at 0.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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