Struct Field Updating and Assignment
Data path registers often hold complex metadata. A status register in a hardware accelerator might track whether a peripheral is ready, if an error has occurred, its operating mode, and the number of active transactions. When an internal fault occurs, the hardware must set an error flag without disturbing the ready state or transaction counts. Conversely, software drivers clear the ready flag without overwriting hardware-managed error flags.
The module maintains an 8-bit packed status register. On reset, it initializes to a ready state with zero errors and a zero count. During normal operation, specific fields are updated based on independent input signals. A hardware signal sets the error flag to 1, a software signal clears the ready flag to 0, and a control signal updates the transaction count to a new value. All these updates can occur in the same clock cycle. If a field is not explicitly updated, it must hold its previous value. The mode field is tied to 0 and never changes.
Clock edge: posedge clk Reset type: Asynchronous active-low rst_n Output values on reset: ready becomes 1; error becomes 0; mode becomes 2'b00; count becomes 4'b0000. Priority rules: Simultaneous updates to different fields are permitted and must all be applied. If rst_n is asserted, it overrides all other inputs.
Cycle 1: rst_n=0 → status_out.ready=1, status_out.error=0, status_out.count=0 Cycle 2: rst_n=1, hw_set_err=1 → status_out.ready=1, status_out.error=1, status_out.count=0 Cycle 3: sw_clr_rdy=1, update_count=1, new_count=5 → status_out.ready=0, status_out.error=1, status_out.count=5 Cycle 4: all inputs 0 → status_out.ready=0, status_out.error=1, status_out.count=5 (hold)
{ "signal": [
{ "name": "clk", "wave": "p......" },
{ "name": "rst_n", "wave": "01....." },
{ "name": "hw_set_err", "wave": "0.100.." },
{ "name": "sw_clr_rdy", "wave": "0..10.." },
{ "name": "update_count", "wave": "0..10.1" },
{ "name": "new_count", "wave": "=.=.=...=", "data": ["0", "5", "9"] },
{},
{ "name": "status_out.ready", "wave": "1..0..." },
{ "name": "status_out.error", "wave": "0.1...." },
{ "name": "status_out.count", "wave": "=.=...=", "data": ["0", "5", "9"] }
], "head": { "text": "Independent field updates to a packed struct register." } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset | | hw_set_err | input | 1 | When 1, sets the error field to 1 | | sw_clr_rdy | input | 1 | When 1, clears the ready field to 0 | | update_count | input | 1 | When 1, updates the count field to new_count | | new_count | input | 4 | The new 4-bit value for the count field | | status_out | output | 8 | The 8-bit packed status struct containing ready (bit 7), error (bit 6), mode (bits 5:4), and count (bits 3:0) |
Constraints
- Reset is asynchronous active-low.
- Updates must occur on the positive edge of
clk. - Simultaneous updates to different fields must be supported in the same clock cycle.
- The
modefield must remain 2'b00 at all times after reset. - Fields not explicitly updated must retain their previous values.
Topics
Solve this problem
Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.