Synchronous Counter with Priority Encoding
Hardware timers and program counters require multiple control signals to manage state. When reset, load, and count commands occur simultaneously, the circuit must enforce a strict priority hierarchy to ensure safe operation.
Construct a 2-bit synchronous up-counter with outputs Q1 and Q0. The counter updates state based on three control signals: rst, load, and en. The control signals must follow a strict priority: rst overrules load, and load overrules en.
| rst | load | en | Next Q1 | Next Q0 | |-------|--------|------|-----------|-----------| | 1 | 0 | 0 | 0 | 0 | | 1 | 0 | 1 | 0 | 0 | | 1 | 1 | 0 | 0 | 0 | | 1 | 1 | 1 | 0 | 0 | | 0 | 1 | 0 | D1 | D0 | | 0 | 1 | 1 | D1 | D0 | | 0 | 0 | 1 | Q1 ⊕ Q0 | ~Q0 | | 0 | 0 | 0 | Q1 | Q0 |
Constraints
- Implement a priority multiplexer chain for the data input of each flip-flop.
- Asserting
rstandloadsimultaneously must result in the next state being 0. - Use standard D flip-flops for state storage.
- Do not use asynchronous reset pins on the flip-flops: all control logic must be synchronous and routed through the D inputs.
Topics
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