The Variable Loop Bound
Software engineers transitioning to RTL frequently attempt to use while loops or for loops with variable bounds to scan data arrays. In a software program, a loop executes sequentially over time. In hardware synthesis, loops must be statically unrolled into parallel combinatorial logic by the synthesizer. A loop condition that depends on an input port cannot be unrolled and will fail synthesis entirely.
The solution module receives an 8-bit input data and must locate the most significant set bit (the highest index where the bit is 1). The output index indicates this position, and the valid signal is asserted. If the input is exactly zero, valid is deasserted and index is set to 0. All outputs are registered.
A software developer might try to write while (temp > 0) { temp >>= 1; count++; }, which is unsynthesizable because the number of iterations depends on the runtime value of data. The correct hardware approach uses a static parallel structure, such as a priority encoder, mapped to sequential outputs.
Timing and Reset Rules
- Clock edge:
posedge clk - Reset type: Asynchronous
- Reset polarity: Active-low (
rst_n) - Output values on reset:
validgoes to 0,indexgoes to 0 - Output timing: All outputs are registered and update one clock cycle after the input is presented
Worked Trace
Cycle 1: rst_n=0 → valid=0, index=0 Cycle 2: rst_n=1, data=8'b0000_1000 → valid=0, index=0 (evaluating) Cycle 3: data=8'b1000_0000 → valid=1, index=3 (result of Cycle 2) Cycle 4: data=8'b0000_0000 → valid=1, index=7 (result of Cycle 3) Cycle 5: data=8'b0110_1101 → valid=0, index=0 (result of Cycle 4) Cycle 6: data=8'b0000_0001 → valid=1, index=6 (result of Cycle 5)
Waveform
{ "signal": [
{ "name": "clk", "wave": "p......" },
{ "name": "rst_n", "wave": "01....." },
{ "name": "data", "wave": "x======", "data": ["8'h08", "8'h80", "8'h00", "8'h6D", "8'h01", "8'hFF"] },
{},
{ "name": "valid", "wave": "0.1.01." },
{ "name": "index", "wave": "0.==0==", "data": ["3", "7", "6", "0"] }
], "head": { "text": "Cycle-by-cycle behavior of the registered priority encoder." } }Port Table
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n| input | 1 | Asynchronous active-low reset; outputs go to 0 when asserted | | data | input | 8 | Input data vector to be scanned | | valid| output | 1 | Asserted if at least one bit in data is set | | index| output | 3 | Index of the most significant set bit (0 to 7); 0 if valid is 0 |
Constraints
- You must use a synthesizable parallel logic structure (static loops or direct boolean logic).
- Do not use
whileloops orforloops bounded by thedatainput. - The
rst_nsignal is asynchronous and active-low. - All outputs must be registered on the positive edge of
clk.
Topics
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