Two Flop Synchronizer Basic Code

Signals crossing asynchronous clock domains frequently cause metastability in receiving registers. A two-flip-flop synchronizer mitigates this risk by providing a full clock cycle of resolution time before the signal is evaluated by downstream logic. This module is the fundamental building block of all clock domain crossing (CDC) paths.

The module accepts an asynchronous input vector and passes it through two cascaded registers clocked by the destination domain clock. The first register captures the asynchronous input, and the second register captures the output of the first. This provides a stable synchronized output exactly two clock cycles after the input stabilizes.

Clocking is driven by clk on the positive edge. The module uses an asynchronous, active-low reset rst_n. On reset, all internal registers and the output evaluate to 0. No combinational logic is permitted between the asynchronous input and the first stage, nor between the first and second stages.

Cycle 1: rst_n=0 → stage1=0, sync_out=0 Cycle 2: rst_n=1, async_in=1 → stage1=0, sync_out=0 (input transitions) Cycle 3: async_in=1 → stage1=1, sync_out=0 (stage1 captures input) Cycle 4: async_in=1 → stage1=1, sync_out=1 (sync_out captures stage1) Cycle 5: async_in=1 → stage1=1, sync_out=1 (steady state) Cycle 6: async_in=0 → stage1=1, sync_out=1 (input transitions) Cycle 7: async_in=0 → stage1=0, sync_out=1 (stage1 captures input) Cycle 8: async_in=0 → stage1=0, sync_out=0 (sync_out captures stage1)

{ "signal": [
  { "name": "clk",       "wave": "p......." },
  { "name": "rst_n",     "wave": "01......" },
  { "name": "async_in",  "wave": "x1...0.." },
  { "name": "stage1",    "wave": "0..1...0" },
  { "name": "sync_out",  "wave": "0...1..." }
], "head": { "text": "Two stage synchronization of an asynchronous pulse." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered destination clock | | rst_n | input | 1 | Asynchronous active-low reset; all outputs and internal states go to 0 when asserted | | async_in | input | WIDTH | Asynchronous input data vector | | sync_out | output | WIDTH | Synchronized output data vector |

Constraints

• Parameter WIDTH must define the bit width of the input and output ports.
• Reset must be asynchronous and active-low.
• All output and internal register bits must evaluate to 0 on reset.
• No combinational logic is allowed; the module must exclusively infer cascaded flip-flops.
• The output sync_out must reflect the captured async_in exactly two clock cycles later.

Topics

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