Valid Ready Pipeline Stage
High-throughput digital systems rely on handshake protocols like AXI-Stream to transfer data between independent modules. Without backpressure, a fast transmitter will overwrite data before a slow receiver can process it. A pipeline stage with valid and ready handshaking isolates timing paths while ensuring zero data loss.
The module acts as a single-element buffer between an upstream source (slave interface) and a downstream sink (master interface). It accepts data when it is empty or when the downstream sink is simultaneously consuming the current data. It asserts its own ready signal upstream based on these conditions. When valid data is accepted, it is stored in an internal register and presented on the output data port alongside the master valid signal.
The circuit is driven by a positive-edge clock and an asynchronous active-low reset. On reset, the internal valid state and data register are cleared to zero. To enable back-to-back same-cycle transfers, the upstream ready signal must be evaluated combinationally.
- Cycle 1:
rst_n=0 →m_valid=0,m_data=0,s_ready=1. - Cycle 2:
rst_n=1,s_valid=1,s_data=A,m_ready=0 →s_ready=1 (empty). Register will load A. - Cycle 3:
s_valid=1,s_data=B,m_ready=0 →m_valid=1,m_data=A,s_ready=0 (full and downstream stalled). Data B is blocked. - Cycle 4:
s_valid=1,s_data=B,m_ready=1 →m_valid=1,m_data=A,s_ready=1 (downstream ready). Register will load B. - Cycle 5:
s_valid=0,s_data=X,m_ready=1 →m_valid=1,m_data=B,s_ready=1. Data B is consumed. - Cycle 6:
s_valid=0,s_data=X,m_ready=0 →m_valid=0,m_data=B (holds last value),s_ready=1. Buffer is empty.
{ "signal": [
{ "name": "clk", "wave": "p......." },
{ "name": "rst_n", "wave": "01......" },
{ "name": "s_valid", "wave": "01110..." },
{ "name": "s_data", "wave": "x==.x...", "data": ["A", "B"] },
{ "name": "m_ready", "wave": "00011..." },
{},
{ "name": "s_ready", "wave": "11011..." },
{ "name": "m_valid", "wave": "001110.." },
{ "name": "m_data", "wave": "00==.0..", "data": ["A", "B"] }
], "head": { "text": "Pipeline filling, stalling, flowing, and draining." } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; clears m_valid and m_data to 0 | | s_valid | input | 1 | Upstream source has valid data available | | s_data | input | 8 | Data from the upstream source | | m_ready | input | 1 | Downstream sink is ready to accept data | | s_ready | output | 1 | Combinational output; asserted if the stage is empty or downstream is ready | | m_valid | output | 1 | Asserted if the stage contains valid data | | m_data | output | 8 | Data currently held in the pipeline stage |
Constraints
- The
s_readyoutput must be evaluated combinationally to allow same-cycle handshaking. - The
m_validandm_dataoutputs must be registered on the positive edge ofclk. m_validandm_datamust reset to 0 asynchronously whenrst_nis 0.m_datamust hold its previous value when the buffer drains (whenm_validgoes low). It should only update when new valid data is actively accepted.
Topics
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