Serial CRC 8 Generator
Every major serial communication protocol relies on a Cyclic Redundancy Check (CRC) to verify data integrity across noisy channels. Hardware CRC generators process incoming bit streams on the fly, calculating a checksum that is verified against the end of a packet to detect transmission errors.
This module computes an 8-bit CRC over a continuous serial data stream using a Galois Linear Feedback Shift Register (LFSR) architecture. The CRC polynomial is $x^8 + x^2 + x + 1$ (0x07). The LFSR shifts and updates its internal state only when the data valid signal is asserted. The module must continuously expose the current CRC value. The boolean logic for the next CRC state (when valid is high) is: • feedback = crc_out[7] ^ data_in • next_crc[0] = feedback • next_crc[1] = crc_out[0] ^ feedback • next_crc[2] = crc_out[1] ^ feedback • next_crc[7:3] = crc_out[6:2]
The module operates on a positive-edge triggered clock (clk) and a synchronous active-low reset (rst_n). On reset, the CRC state initializes to 8'h00. When data_valid is high, the CRC state updates on the next rising clock edge. When data_valid is low, the CRC state holds its previous value. The output crc_out is registered and reflects the current state of the LFSR.
Cycle 1: rst_n=0 → crc_out=8'h00 Cycle 2: rst_n=1, data_valid=1, data_in=1 → feedback=1, crc_out=8'h07 Cycle 3: rst_n=1, data_valid=1, data_in=0 → feedback=0, crc_out=8'h0E Cycle 4: rst_n=1, data_valid=0, data_in=1 → crc_out=8'h0E (hold) Cycle 5: rst_n=1, data_valid=1, data_in=1 → feedback=1, crc_out=8'h1B
{ "signal": [
{ "name": "clk", "wave": "p........." },
{ "name": "rst_n", "wave": "01........" },
{ "name": "data_valid", "wave": "01101....." },
{ "name": "data_in", "wave": "x10x1....." },
{ "name": "crc_out", "wave": "=.====....", "data": ["00", "00", "07", "0E", "0E", "1B"] }
], "head": { "text": "Cycle-by-cycle CRC computation with data valid gaps." } }| Signal | Direction | Width | Description | |---|---|---|---| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Synchronous active-low reset; initializes CRC to 8'h00 | | data_valid | input | 1 | High when data_in is valid | | data_in | input | 1 | Serial data input bit | | crc_out | output | 8 | Current registered CRC value |
Constraints
- The clock edge is
posedgeand reset is synchronous active-low. - Output
crc_outmust be 8'h00 on reset. - Reset has priority over
data_valid. - Output
crc_outmust be driven by a register, not combinational logic. - The module must not update its state when
data_validis 0.
Topics
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