Why One FF Is Insufficient for Synchronization
Two positive-edge-triggered D flip-flops are connected in series: Q1 samples ASYNC_IN, and Q2 samples Q1. Four signals are shown: CLK (clock, period 8), ASYNC_IN (asynchronous input), Q1 (first stage output, initially 0), and Q2 (second stage output, initially 0). If a flip-flop's input changes at the exact same time step as a CLK LOW-to-HIGH transition, its output becomes metastable (X). Assume metastability on Q1 resolves to a stable 1 at time step 10. Trace both Q1 and Q2 across all 16 time steps.
Constraints
- Use
Xfor any time step where a signal is metastable. - Assume the flip-flops have zero propagation delay and sample the value present immediately prior to the clock edge.
Topics
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