3-Bit Johnson Counter
Glitch-free multiphase clock generation and digital position encoders rely on twisted ring counters to produce overlapping wave patterns. The Johnson counter is a specialized shift register that produces exactly 2N states for an N-bit width, avoiding the decoding spikes of standard binary counters.
Construct a 3-bit Johnson counter with an active-high synchronous reset. The outputs Q2, Q1, and Q0 must shift right on each active clock edge. The inverted output of the final stage Q0 feeds back into the first stage Q2.
| Cycle | rst | Q2 | Q1 | Q0 | |-------|-------|------|------|------| | 0 | 1 | 0 | 0 | 0 | | 1 | 0 | 1 | 0 | 0 | | 2 | 0 | 1 | 1 | 0 | | 3 | 0 | 1 | 1 | 1 | | 4 | 0 | 0 | 1 | 1 | | 5 | 0 | 0 | 0 | 1 | | 6 | 0 | 0 | 0 | 0 |
Constraints
- Use exactly three D flip-flops.
- Implement a synchronous active-high reset.
- Do not use any external combinational logic other than the feedback inverter.
Topics
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