4-Bit LFSR Pseudo-Random Counter
Hardware security modules, test pattern generators, and communication scramblers rely on pseudo-random bit sequences. The Linear Feedback Shift Register (LFSR) generates these sequences using specific feedback polynomials to guarantee maximal length without repeating prematurely.
Implement a 4-bit LFSR using the primitive polynomial x^4 + x + 1. The circuit must maintain a 4-bit output bus Q. At each rising edge of clk, the register shifts right: Q[2] receives Q[3], Q[1] receives Q[2], and Q[0] receives Q[1]. The new bit entering Q[3] must be the XOR of the current Q[3] and Q[0] taps.
Choosing incorrect taps, such as Q[3] and Q[2], produces a non-maximal-length sequence. The specified primitive polynomial guarantees a full 15-cycle period before repeating.
| rst | clk | Q (Current) | Q (Next) | |-------|-------|---------------|------------| | 1 | X | X | 1 | | 0 | ↑ | 1 | 8 | | 0 | ↑ | 8 | 12 | | 0 | ↑ | 12 | 14 | | 0 | ↑ | 14 | 15 | | 0 | ↑ | 15 | 7 |
Constraints
- Use standard D flip-flops for the state register.
- Implement exactly one XOR gate for the feedback path.
- Shift the data linearly from
Q[3]down toQ[0]. - Implement an asynchronous active-high
rstsignal that forcesQto1(binary0001).
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.