4-Bit Up/Down Counter Using D Flip-Flops: K-Map Derivation
Bi-directional state machines appear in PWM controllers, motor position trackers, and reversible timers. A 4-bit up/down counter built from D flip-flops requires full next-state derivation rather than the simple toggle conditions used in T flip-flop designs.
The circuit must track a 4-bit state Q consisting of Q3, Q2, Q1, and Q0. It increments by one on the rising clock edge when dir is 1, and decrements by one when dir is 0. A synchronous active-high rst signal forces the state to 0000.
Because the next state depends on the current state and the direction, the D flip-flop excitation equations require evaluating a 5-variable logic function. The table below outlines key state transitions.
| dir | Q3 | Q2 | Q1 | Q0 | D3 | D2 | D1 | D0 | |-------|------|------|------|------|------|------|------|------| | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |
Constraints
- Use exactly four D flip-flops.
- Implement the next-state logic using basic combinational gates (AND, OR, NOT, XOR).
- Do not use pre-built counter modules or arithmetic adders.
- Implement
rstas a synchronous active-high reset.
Topics
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