Up/Down Counter: DOWN Mode Counting UP Debug
Up/down counters track position in rotary encoders and bi-directional inventory systems.
A 2-bit up/down counter increments its value on the rising clock edge when DOWN=0 and decrements when DOWN=1. An asynchronous reset rst clears the counter to 00.
Expected behavior:
| DOWN | Current Q1 | Current Q0 | Next Q1 | Next Q0 | |--------|--------------|--------------|-----------|-----------| | 0 | 0 | 0 | 0 | 1 | | 0 | 0 | 1 | 1 | 0 | | 0 | 1 | 0 | 1 | 1 | | 0 | 1 | 1 | 0 | 0 | | 1 | 0 | 0 | 1 | 1 | | 1 | 1 | 1 | 1 | 0 | | 1 | 1 | 0 | 0 | 1 | | 1 | 0 | 1 | 0 | 0 |
Simulation shows the counter increments regardless of the DOWN signal. When initialized to 00 with DOWN=1, the next state evaluates to 01 instead of 11. Inspect the circuit and correct the fault.
Constraints
- Do not modify the clock or reset routing.
- Preserve the existing flip-flop components.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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