4-Bit Up/Down Counter with Parallel Load
Programmable timers and sequence generators require counters that can be initialized to an arbitrary value and stepped in either direction. The 4-bit up/down counter with parallel load provides full state control via a priority-encoded command interface.
At each rising clock edge, the 4-bit output Q updates to a new state Q_next based on the control signals. The load command has the highest priority and overwrites the current state with the parallel data input D. If load is not asserted, up dictates forward counting and down dictates reverse counting. The counter wraps around upon overflow or underflow.
| load | up | down | Q_next | |--------|------|--------|----------| | 1 | X | X | D | | 0 | 1 | X | Q + 1 | | 0 | 0 | 1 | Q - 1 | | 0 | 0 | 0 | Q |
Constraints
- Use positive edge-triggered D flip-flops for the state registers.
- Implement priority routing using multiplexers or standard combinational logic gates.
- Do not use pre-packaged counter or arithmetic logic unit (ALU) blocks.
Topics
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