Up/Down Counter: Direction Change at Terminal Count
A positive-edge-triggered 4-bit synchronous up/down counter increments its value when UP_DN is 1 and decrements when UP_DN is 0 at each LOW-to-HIGH transition of CLK.
Six signals are shown: CLK (clock, period 2), UP_DN (direction control input), and Q3, Q2, Q1, Q0 (outputs, initially 1110). Q3 represents the most significant bit.
Trace Q3, Q2, Q1, and Q0 across all 12 time steps.
Constraints
- The counter wraps around at its limits: 15 increments to 0, and 0 decrements to 15.
- The direction input
UP_DNis evaluated exactly at the rising edge ofCLK.
Topics
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