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Codiode/Problems/Sequential Logic

8-Bit Serial Link with Byte Misalignment Debug

HardLogic CircuitDebug

An 8-bit serial link receiver deserializes an incoming bitstream into parallel bytes.

Expected behavior:

The receiver waits for a start bit (a 1 to 0 transition on Rx), shifts in 8 data bits, and asserts Valid for one clock cycle while outputting the aligned byte on DataOut.

Simulation shows that the receiver is systematically misaligned. When transmitting 0xAB (binary 10101011), the receiver outputs 0x56 (binary 01010110). When transmitting 0xCD (binary 11001101), the receiver outputs 0xE6 (binary 11100110). Every received byte is a 1-bit rotation of the transmitted byte, indicating a consistent framing error rather than random data corruption. Inspect the circuit and correct the fault.

Constraints

  • Only modify the synchronization and start-bit detection logic.
  • Do not change the datapath of the 8-bit shift register.
  • The circuit must correctly identify the falling edge of the start bit before beginning the shift sequence.

Topics

DebugSynchronizationShift RegistersUART

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