AND Gate Clock Gating Glitches
Clock gating circuits disable the clock signal to inactive blocks to minimize power consumption. A safe clock gating cell must output a clean clock signal GCLK when EN is high and hold GCLK low when EN is low, without introducing glitches.
Expected behavior:
| Step | CLK | EN | GCLK | Notes | |------|-------|------|--------|-------| | 1 | 0 | 0 | 0 | Clock low, disabled | | 2 | 0 | 1 | 0 | Enable rises while clock is low | | 3 | 1 | 1 | 1 | Clock high, enabled | | 4 | 1 | 0 | 1 | Enable falls while clock is high. GCLK must complete the pulse. | | 5 | 0 | 0 | 0 | Clock falls |
Simulation shows GCLK = 0 at Step 4. The downstream state machine registers an illegal state transition due to a runt pulse on the clock net. Inspect the circuit and correct the fault.
Constraints
- Do not modify the downstream flip-flops.
- The fix must use a memory element to prevent
ENfrom propagating whileCLKis high.
Topics
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