Asynchronous Assertion and Synchronous Deassertion

Every digital system requires a reliable reset mechanism to initialize state safely. When an external reset signal originates from a button press, a power-on-reset circuit, or a different clock domain, its deassertion might violate the setup or hold time of flip-flops in the destination domain. This violation causes metastability, potentially bringing parts of the system out of reset while others remain stuck. A standard reset synchronizer solves this by guaranteeing the reset asserts asynchronously to protect the circuit immediately, but deasserts synchronously with the destination clock to prevent recovery time violations.

The module accepts an external asynchronous active-low reset and synchronizes it to a local clock domain. When the external reset is asserted low, the synchronized output must immediately drop low without waiting for a clock edge. When the external reset is deasserted high, the synchronized output remains low until it safely propagates through a two-stage synchronization chain. The output only returns high after two consecutive rising clock edges following the deassertion of the external reset.

Timing and Reset Rules: • Clock edge: Positive-edge triggered clk • Reset type: Asynchronous, active-low rst_async_n • Output behavior on reset: The output rst_sync_n goes to 0 immediately when rst_async_n is 0, regardless of the clock state. • Normal operation: Once rst_async_n is released to 1, a logic 1 must propagate through two sequential flip-flops. • Registered output: The output rst_sync_n is driven directly by the second flip-flop in the synchronization chain.

Worked Trace: Cycle 1: rst_async_n=0, clk=0 → rst_sync_n=0 (Asynchronous assertion immediately clears output) Cycle 2: rst_async_n=1, clk=0 → rst_sync_n=0 (Reset deasserted, but output held low waiting for clock) Cycle 3: rst_async_n=1, clk=1 → rst_sync_n=0 (First positive clock edge captures high state in first stage) Cycle 4: rst_async_n=1, clk=0 → rst_sync_n=0 (Output remains low) Cycle 5: rst_async_n=1, clk=1 → rst_sync_n=1 (Second positive clock edge captures high state in second stage; synchronous deassertion complete)

{ "signal": [
  { "name": "clk",         "wave": "0.p......." },
  { "name": "rst_async_n", "wave": "01........" },
  { "name": "rst_sync_n",  "wave": "0...1....." }
], "head": { "text": "Asynchronous assertion and two-cycle synchronous deassertion." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Destination clock domain, positive-edge triggered | | rst_async_n | input | 1 | Asynchronous active-low reset from source domain | | rst_sync_n | output | 1 | Synchronized active-low reset for destination domain |

Constraints

• The output rst_sync_n must assert asynchronously when rst_async_n is 0.
• The output rst_sync_n must deassert synchronously on the positive edge of clk.
• The synchronization chain must be exactly two stages deep.
• Do not use latches.

Topics

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