Reset Synchronizer Tree

Modern system-on-chips feature clock domains containing hundreds of thousands of flip-flops. A single reset synchronizer cannot drive this massive load without violating timing constraints due to high fanout and routing delays. To resolve this, physical design teams use a reset tree; the asynchronous reset is first synchronized, and then pipelined and duplicated to drive regional reset buffers.

The reset_sync_tree module takes an asynchronous active-low reset and a destination clock. It must safely synchronize the reset de-assertion to the destination clock domain and distribute it across a 4-branch pipeline.

To meet the architectural requirements, your design must implement exactly three stages of flip-flops: • Stage 1: A single synchronizer flip-flop that samples a constant 1'b1 on the positive edge of the clock. • Stage 2: A single flip-flop that samples the output of Stage 1. • Stage 3: Four parallel flip-flops that all sample the output of Stage 2. These drive the 4-bit output vector.

All flip-flops in the design must be asynchronously reset by the incoming reset signal. When the reset is asserted, all outputs must immediately drop to 0. When the reset is de-asserted, the release propagates through the shift register taking exactly three clock cycles to reach the outputs.

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Destination clock domain | | async_rst_n | input | 1 | Asynchronous active-low reset | | sync_rst_n | output | 4 | Four duplicated, synchronized active-low reset signals |

Constraints

• All flip-flops must be asynchronously reset by async_rst_n.
• Output sync_rst_n must be registered.
• The design must use exactly 3 stages of flip-flops from the internal constant 1'b1 to the output.
• Stage 1 and Stage 2 must be single flip-flops.
• Stage 3 must consist of four parallel flip-flops driving sync_rst_n.
• The outputs must transition to 4'b0000 immediately when async_rst_n goes low.

Topics

Related problems

• Basic D Flip FlopEasy
• Asymmetric Clock DividerHard
• SystemVerilog Assertions for Clock Domain CrossingHard
• Reversing a Bit VectorEasy
• Debug: Blocking Assignment Race ConditionMedium
• Always Latch Intentional DesignMedium
• First Word Fall Through FIFO WrapperHard
• The Variable Loop BoundMedium