Coordinated Reset Sequence

In complex System-on-Chip designs, the data path domain must often be held in reset until the control domain has fully initialized to prevent spurious transactions. A coordinated reset sequencer ensures that multiple clock domains come out of reset in a strict, deterministic order, preventing unpredictable behaviour at power-on.

The module receives a global asynchronous active-low reset. When asserted, both Domain A and Domain B resets are driven low immediately. When the global reset is released, Domain A's reset is deasserted synchronously to its own clock. The sequencer then waits for Domain A to be fully out of reset, synchronizes this state into Domain B's clock domain, and waits exactly ten clock cycles of Domain B before synchronously releasing Domain B's reset.

Timing and Reset Rules: • Clocks clk_a and clk_b are positive-edge triggered and completely asynchronous to each other. • Global reset rst_ni is asynchronous and active-low. • rst_a_n must assert (go to 0) asynchronously the moment rst_ni goes to 0. It must deassert (go to 1) synchronously on the second positive edge of clk_a after rst_ni is released. • rst_b_n must assert asynchronously the moment rst_ni goes to 0. • To release rst_b_n, the rst_a_n signal must first be synchronized into the clk_b domain using a 2-stage flip-flop synchronizer. • Once the second stage of the clk_b synchronizer outputs a 1, a counter increments on each subsequent positive edge of clk_b. • Exactly on the 10th positive edge of clk_b where the synchronized rst_a_n is 1, rst_b_n transitions to 1.

Worked Trace: • Cycle 1: rst_ni=0 → rst_a_n=0, rst_b_n=0 • Cycle 2: rst_ni=1, clk_a posedge → sync_a_1=1, rst_a_n=0 • Cycle 3: clk_a posedge → rst_a_n=1 (Domain A released) • Cycle 4: clk_b posedge → sync_b_1=1 (sampling rst_a_n) • Cycle 5: clk_b posedge → sync_b_2=1 (synchronized into Domain B) • Cycle 6: clk_b posedge → count=1 • Cycle 7: clk_b posedge → count=2 • ... • Cycle 14: clk_b posedge → count=9 • Cycle 15: clk_b posedge → count=10, rst_b_n=1 (Domain B released)

{ "signal": [
  { "name": "rst_ni",  "wave": "01.............." },
  { "name": "clk_a",   "wave": "p..............." },
  { "name": "rst_a_n", "wave": "0.1............." },
  { "name": "clk_b",   "wave": "p..............." },
  { "name": "sync_b2", "wave": "0...1..........." },
  { "name": "count",   "wave": "====.=.=.====.==", "data": ["0", "0", "1", "2", "9", "10"] },
  { "name": "rst_b_n", "wave": "0..............1" }
],
"head": { "text": "Domain A releases, then Domain B waits 10 cycles." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk_a | input | 1 | Clock for Domain A; positive-edge triggered | | clk_b | input | 1 | Clock for Domain B; positive-edge triggered | | rst_ni | input | 1 | Global asynchronous active-low reset | | rst_a_n | output | 1 | Domain A reset; asserts asynchronously, deasserts synchronously to clk_a | | rst_b_n | output | 1 | Domain B reset; asserts asynchronously, deasserts synchronously to clk_b after 10-cycle delay |

Constraints

• Both rst_a_n and rst_b_n must go to 0 asynchronously when rst_ni is 0.
• rst_a_n must be generated using a 2-stage synchronizer clocked by clk_a with its input tied to 1.
• rst_a_n must be synchronized into the clk_b domain using a 2-stage synchronizer clocked by clk_b.
• The 10-cycle delay in Domain B must be counted only when the 2nd stage of the clk_b synchronizer is 1.
• The counter must not overflow; it must hold its value once rst_b_n is asserted.
• Every flip-flop in the design must use rst_ni as an asynchronous active-low reset.

Topics

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