Divide by Two Clock Generator
Peripheral interfaces often operate at lower frequencies than the main system clock, requiring reliable clock division schemes. This module divides an incoming clock frequency by two, producing an output clock with a 50% duty cycle. It achieves this by toggling its output state on every active edge of the source clock.
The divider uses a single flip-flop that feeds its inverted output back into its own input. This ensures the output state alternates cleanly on every clock cycle without requiring external counters.
- Clock edge:
posedge clk_in - Reset type: Asynchronous
- Reset polarity: Active-low (
rst_n) - Output value on reset:
clk_outmust be0 - Priority rules: Asynchronous reset takes highest priority over clock edges
Cycle 1: rst_n=0 → clk_out=0 Cycle 2: rst_n=1, clk_in rises → clk_out=1 Cycle 3: rst_n=1, clk_in rises → clk_out=0 Cycle 4: rst_n=1, clk_in rises → clk_out=1
{ "signal": [
{ "name": "clk_in", "wave": "p......." },
{ "name": "rst_n", "wave": "01......" },
{ "name": "clk_out", "wave": "01010101" }
], "head": { "text": "Clock divided by two with 50% duty cycle." } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk_in | input | 1 | Positive-edge triggered source clock | | rst_n | input | 1 | Asynchronous active-low reset; drives clk_out to 0 | | clk_out | output | 1 | Divided clock output |
Constraints
- Clock edge must be
posedge clk_in. - Reset must be asynchronous and active-low.
clk_outmust be exactly0on reset.clk_outmust be a registered output directly driven by a flip-flop.- No combinational logic is permitted on the output clock path to avoid glitches.
Topics
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