Asynchronous FIFO Pointer Gray Code Verification
Asynchronous FIFO pointers use Gray code sequences to safely transfer state across clock domains without multi-bit glitches.
Expected behavior:
| Reset | Clk (edge) | G1 | G0 | |---------|--------------|------|------| | 1 | X | 0 | 0 | | 0 | 1 | 0 | 1 | | 0 | 2 | 1 | 1 | | 0 | 3 | 1 | 0 | | 0 | 4 | 0 | 0 |
Simulation shows G1 = 1 and G0 = 0 on the second clock edge after reset. The pointer is generating a standard binary sequence instead of Gray code, which introduces glitch hazards on the clock domain crossing. Inspect the circuit and correct the fault.
Constraints
- The outputs
G1andG0must be driven directly by flip-flop outputs to ensure glitch-free crossing. - No combinational logic is permitted between the flip-flops and the output ports.
- Use only standard logic gates (AND, OR, NOT, XOR) and D flip-flops.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.