Asynchronous Reset Missing from Sensitivity List
A data path register stores a single bit of information and clears its output immediately upon an active-low reset.
Expected behavior:
When rst_n is 0, the output q must immediately become 0 regardless of the clock clk state. When rst_n is 1, the output q updates to the value of input d on the rising edge of clk.
Simulation shows q = 1 when rst_n = 0 and clk = 0 after the register was previously loaded with a 1. The output fails to clear asynchronously and instead waits for the next clock edge. Inspect the circuit and correct the fault.
Constraints
- Do not modify the port list of the module.
- The reset behavior must be strictly asynchronous.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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