Asynchronous Reset Wired as Synchronous Reset
A D flip-flop with an asynchronous reset clears the output immediately when the reset signal is asserted, independent of the clock state.
Expected behavior:
| CLK | D | RST | Q (next) | |-------|-----|-------|------------| | X | X | 1 | 0 | | ↑ | 0 | 0 | 0 | | ↑ | 1 | 0 | 1 | | 0/1 | X | 0 | Q (hold) |
Simulation shows Q remaining at 1 when RST is asserted while CLK is 0. The output Q only transitions to 0 at the next positive edge of CLK. The reset is taking effect one cycle late. Inspect the circuit and correct the fault.
Constraints
- Do not modify the core latch structures of the flip-flop.
- Only correct the routing of the
RSTsignal.
Topics
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