Asynchronous Reset Glitch
A registered output Q captures data D on the rising edge of Clk and clears to 0 when external signals A and B are both high.
Expected behavior:
The output Q updates only on the rising edge of Clk. If A and B are both 1 at the rising edge of Clk, Q becomes 0. Otherwise, Q takes the value of D.
Simulation shows Q dropping to 0 unexpectedly between clock cycles. Specifically, when Q is 1 and Clk is 0, a simultaneous transition of A from 1 to 0 and B from 0 to 1 causes Q to instantly clear to 0. The output is incorrectly resetting due to transient signal states. Inspect the circuit and correct the fault.
Constraints
- The reset behavior must be fully synchronous to
Clk. - Do not use the asynchronous reset or clear pins on any flip-flop.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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