AXI Stream Valid Ready Dropped Data
An AXI Stream pipeline stage buffers data and manages flow control between upstream and downstream components.
Expected behavior: The stage must capture s_data into m_data and assert m_valid when s_valid is high and the stage is ready. It must hold m_data and m_valid steady if the downstream m_ready signal is low. The stage asserts s_ready when it is empty or when the downstream component is accepting the current data.
Simulation shows data corruption during backpressure. When m_ready is low and a new s_valid transaction arrives, the pipeline overwrites m_data with the new input instead of holding the stalled data. Inspect the circuit and correct the fault.
Constraints
- Do not add any new flip-flops to the circuit.
- The circuit must maintain a one-cycle latency through the pipeline stage.
- You may only modify the combinational logic driving the register enable pins.
Topics
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