Back of Envelope Maximum Frequency
Static timing analysis determines whether a digital design will function correctly at a target clock speed before a single transistor is fabricated. The circuit contains three flip-flops: FF1, FF2, and FF3. All flip-flops share a common clock CLK with zero skew.
The flip-flop timing parameters are T_cq = 0.3 ns and T_setup = 0.2 ns. The combinational logic between FF1 and FF2 consists of an AND gate with a delay of 0.2 ns followed by an XOR gate with a delay of 0.3 ns. The logic between FF2 and FF3 is a single inverter with a delay of 0.1 ns. An asynchronous external input EXT routes through a complex combinational block with a 2.5 ns delay directly into the D pin of FF3.
Calculate the maximum operating frequency of this synchronous circuit. Identify the true critical path and determine the limiting delay.
Constraints
- All time values are in nanoseconds (ns).
- Clock skew and jitter are assumed to be zero unless otherwise specified.
EXTis asynchronous and not launched by theCLKdomain.
Topics
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