Back of Envelope FIFO Sizing
Asynchronous FIFOs bridge clock domains by safely absorbing bursts of data without dropping words.
The system under analysis contains a transmit block operating on a 100 MHz write clock clk_w and a receive block operating on an 80 MHz read clock clk_r. The transmitter sends data in continuous bursts of 120 words. During a burst, one word is written to the FIFO every clk_w cycle. The receiver can read one word every clk_r cycle as long as the FIFO is not empty.
Calculate the minimum safe FIFO depth to prevent overflow during a maximum burst.
Constraints
- Assume no idle cycles occur between word writes during a single burst.
- Assume the FIFO is completely empty at the start of the burst.
- Assume the receiver begins reading immediately once the first word is available.
Topics
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