Basic Rising Edge Detector
Raw external signals must be converted to single cycle pulses to trigger internal state machines reliably. This prevents long-held inputs from causing multiple unintended state transitions.
The circuit monitors a synchronous input din and generates a single-cycle high pulse on pulse_out immediately following a 0 to 1 transition. The output must remain high for exactly one clock cycle, regardless of how long din remains high.
| Cycle | din | pulse_out | |-------|-------|-------------| | 1 | 0 | 0 | | 2 | 1 | 1 | | 3 | 1 | 0 | | 4 | 0 | 0 |
Constraints
- Use a D flip-flop to store the state of the input from the previous clock cycle.
- Implement an active-high synchronous reset using the
rstsignal. - Clear all internal state to 0 when
rstis high. - Generate
pulse_outusing combinational logic based on the current input and the stored previous input.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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