Basic Falling Edge Detector
Communication protocols like UART and I2C rely on detecting a high-to-low transition on the data line to signal the start of a transaction. A synchronous edge detector safely flags this event for exactly one clock cycle without introducing combinational glitches.
The circuit must monitor the din signal and assert pulse to 1 during the exact clock cycle that a 1-to-0 transition is detected. The detection compares the current state of din against its state from the previous clock cycle.
| din (previous) | din (current) | pulse | |------------------|-----------------|---------| | 0 | 0 | 0 | | 0 | 1 | 0 | | 1 | 0 | 1 | | 1 | 1 | 0 |
Constraints
- Use exactly one D flip-flop to store the previous state of the input.
- Derive the output using only the current input and the registered previous input.
- Do not use asynchronous delay chains or series inverters to create timing delays.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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