BCD Counter: Full Decade Waveform
A positive-edge-triggered BCD (Binary-Coded Decimal) counter increments its 4-bit output by one on every LOW-to-HIGH transition of CLK when EN is HIGH, rolling over to 0000 immediately after reaching 1001 (9).
Six signals are shown: CLK (clock, period 2), EN (count enable input), and Q3, Q2, Q1, Q0 (outputs, initially 0000).
Trace the outputs Q3, Q2, Q1, and Q0 across all 24 time steps to demonstrate a full decade count and the subsequent reset cycle.
Constraints
- The state transitions strictly on the LOW-to-HIGH edge of
CLK. - The counter must never enter state 10 (1010).
Q3is the most significant bit (8s place) andQ0is the least significant bit (1s place).
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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