BCD Decade Counter: Synchronous Reset Construction
Digital clocks, frequency dividers, and multi-digit displays rely on binary-coded decimal (BCD) counters to track base-10 values. The decade counter truncates a standard 4-bit binary sequence to a modulus of 10.
Implement a 4-bit synchronous BCD decade counter. On every clock cycle where rst is 0, the counter increments. It must count from 0 to 9 (binary 0000 to 1001). When the counter reaches 9, the next state must wrap around to 0. When rst is 1, the counter synchronously resets to 0000.
| rst | Current Q | Next Q | |-------|-------------|----------| | 1 | X | 0 | | 0 | 0 to 8 | Q + 1 | | 0 | 9 | 0 |
Constraints
- Use only synchronous logic for the state updates.
- The counter must strictly output the sequence 0 through 9 and wrap back to 0.
- Do not use asynchronous clears to force the wrap-around.
Topics
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