Up/Down Counter: Enable Direction Latch
A positive-edge-triggered 2-bit counter increments when DIR is 1 and decrements when DIR is 0, but only updates its state when EN is 1.
Five signals are shown: CLK (clock, period 2), EN (active-high enable), DIR (direction control), and Q1 and Q0 (the 2-bit output state, both initially 0).
Trace Q1 and Q0 across all 12 time steps.
Constraints
- The counter state only updates on the LOW-to-HIGH transition of
CLK. - Changes to
DIRwhileENis 0 do not immediately affect the output but dictate the direction of the next active count.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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