Up/Down Counter with 7-Segment Display
Digital clocks, microwave timers, and instrumentation panels require human-readable numeric outputs. This subsystem links a state-tracking sequential core directly to a combinational display driver.
The circuit integrates a modulo-10 (BCD) counter and an active-high 7-segment decoder. The internal counter tracks decimal values from 0 to 9. When rst is 1, the internal count synchronously resets to 0. When rst is 0, the counter increments on the clock edge if up_down is 1, and decrements if up_down is 0. The counter must wrap around: incrementing past 9 rolls over to 0, and decrementing past 0 rolls under to 9. The outputs a through g drive the 7-segment display corresponding to the current internal decimal value.
| Value | a | b | c | d | e | f | g | |---------|-----|-----|-----|-----|-----|-----|-----| | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | | 2 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | | 3 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | | 4 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | | 5 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | | 6 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | | 7 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | | 8 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | | 9 | 1 | 1 | 1 | 1 | 0 | 1 | 1 |
Constraints
- Implement a synchronous reset for the counter.
- Restrict the internal count strictly to the 0 to 9 range.
- Use active-high logic for all 7-segment outputs.
- Derive the display outputs combinatorially from the counter state.
Topics
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