Up/Down Counter: Underflow Detection Missing Debug
Cascaded down-counters rely on a borrow out signal to trigger the next stage when decrementing past zero. A 4-bit up/down counter must assert the BOUT signal when the current count is 0000 and the count direction signal DOWN is active.
Expected behavior:
When DOWN is 1 and the count state Q3, Q2, Q1, Q0 is 0, 0, 0, 0, the output BOUT must be 1. For all other states during a countdown, BOUT must be 0. When DOWN is 0, BOUT must always be 0.
Simulation shows a failure during the countdown sequence. As the counter passes through states 0001, 0000, and 1111, the BOUT signal remains 0. Inspect the circuit and correct the fault.
Constraints
- Do not modify the sequential logic or flip-flops.
- Only correct the combinational logic driving the
BOUToutput. - The counter must maintain standard positive-edge triggered behavior.
Topics
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