Up/Down Counter: Saturating Mode
A positive-edge-triggered 4-bit saturating counter increments when UP is high and decrements when DOWN is high, but holds its value at maximum (1111) and minimum (0000) to prevent rollover. Seven signals are shown: CLK (clock, period 2), UP (count up enable), DOWN (count down enable), and the four output bits Q3, Q2, Q1, and Q0 (initially 1101). Trace the output bits Q3, Q2, Q1, and Q0 across all 16 time steps.
Constraints
- The counter updates its state only on the LOW-to-HIGH transition of
CLK. - When the counter reaches 1111, further
UPassertions are ignored and the count remains 1111.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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