BCD Counter Sequence Error
A BCD (Binary-Coded Decimal) counter tracks digits from 0 to 9 and resets to 0 on the tenth clock cycle.
Expected behavior:
| State | Q3 | Q2 | Q1 | Q0 | |-------|------|------|------|------| | 0 | 0 | 0 | 0 | 0 | | 1 | 0 | 0 | 0 | 1 | | 2 | 0 | 0 | 1 | 0 | | 3 | 0 | 0 | 1 | 1 | | 4 | 0 | 1 | 0 | 0 | | 5 | 0 | 1 | 0 | 1 | | 6 | 0 | 1 | 1 | 0 | | 7 | 0 | 1 | 1 | 1 | | 8 | 1 | 0 | 0 | 0 | | 9 | 1 | 0 | 0 | 1 | | 10 (Resets to 0) | 0 | 0 | 0 | 0 |
Simulation shows the count sequence proceeding normally past 9. The counter reaches 11 (binary 1011) and then resets to 0 on the twelfth clock pulse. The counting period is incorrect because the terminal state is wrong.
Inspect the circuit and correct the fault.
Constraints
- Do not add new logic gates or components.
- Only modify the wiring of the reset decoding logic.
- The counter must reset asynchronously exactly when it reaches state 10.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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