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Codiode/Problems/Sequential Logic

BCD Counter: State 12 Lockup Debug

HardLogic CircuitDebug

A BCD counter increments through binary states 0 to 9 and resets to 0.

Expected behavior:

| Q3 | Q2 | Q1 | Q0 | D3 | D2 | D1 | D0 | |------|------|------|------|------|------|------|------| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |

Simulation of abnormal power-on states reveals a lockup condition. When the circuit initializes with Q3=1, Q2=1, Q1=0, Q0=0 (state 12), the next-state logic evaluates to D3=1, D2=1, D1=0, D0=0. The counter remains stuck in state 12 across all subsequent clock cycles.

Inspect the circuit and correct the fault.

Constraints

  • The circuit must maintain the valid 0 through 9 counting sequence.
  • The circuit must recover from state 12 by transitioning to state 0 on the next clock cycle.
  • Do not add unnecessary gates to paths that already function correctly.

Topics

BCDDebugCountersState Machines

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