BCD Counter: Self-Correction from Invalid States
Safety-critical industrial timers and medical devices cannot rely on undefined behavior for invalid states. A robust Binary-Coded Decimal (BCD) counter requires explicit next-state logic to guarantee that if a transient fault forces it into an invalid state, it recovers to a valid state on the very next clock cycle.
The circuit implements the next-state logic for a self-correcting BCD counter. It calculates the next state (D3, D2, D1, D0) from the current state (Q3, Q2, Q1, Q0). For valid BCD states (0 to 9), the counter increments normally and wraps from 9 to 0. For invalid states (10 to 15), the logic must enforce a strict recovery sequence: 10 recovers to 0, 11 recovers to 1, 12 recovers to 0, 13 recovers to 1, 14 recovers to 0, and 15 recovers to 0.
| Q3 | Q2 | Q1 | Q0 | D3 | D2 | D1 | D0 | |------|------|------|------|------|------|------|------| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 |
Constraints
- Implement only the combinational next-state logic.
- Do not use sequential elements like flip-flops or latches.
- Treat all 16 input combinations as explicit requirements with no don't-care conditions.
Topics
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