Two-Digit BCD Counter
Digital timers, industrial counters, and instrumentation displays rely on multi-digit decimal counting. Cascading single-digit units creates an N-digit decimal counter where the terminal count of a lower significant digit enables the increment of the next higher digit.
The circuit must implement a synchronous 00 to 99 BCD (Binary-Coded Decimal) counter. The 4-bit q_ones output increments on every rising edge of the clock when en is high. When q_ones reaches 9, it must roll over to 0 on the next active clock edge, and simultaneously, the 4-bit q_tens output must increment. When the overall count reaches 99 (q_tens = 9, q_ones = 9), both digits must roll over to 0 on the next active clock edge. An active-low synchronous reset_n forces both digits to 0 on the next clock edge, overriding the en signal.
| reset_n | en | q_tens (current) | q_ones (current) | q_tens (next) | q_ones (next) | |-----------|------|--------------------|--------------------|-----------------|-----------------| | 0 | X | X | X | 0 | 0 | | 1 | 0 | X | X | q_tens | q_ones | | 1 | 1 | 0 | 8 | 0 | 9 | | 1 | 1 | 0 | 9 | 1 | 0 | | 1 | 1 | 9 | 8 | 9 | 9 | | 1 | 1 | 9 | 9 | 0 | 0 |
Constraints
- Logic must be fully synchronous to the rising edge of the clock.
- Use positive edge-triggered D flip-flops for all state elements.
- The
reset_nsignal must route to the synchronous reset logic of both digits simultaneously. - Do not use behavioral counter blocks; construct the counting logic using standard combinational gates and flip-flops.
Topics
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