Bidirectional SR: Direction Change Mid-Pattern Waveform
A 4-bit bidirectional shift register updates its state on the positive edge of CLK according to the LOAD and DIR control signals.
Seven signals are defined for this circuit: CLK (clock, period 2), LOAD (active-high synchronous load), DIR (direction control: 1 for right shift, 0 for left shift), and outputs Q3, Q2, Q1, Q0 (initially all 0). The parallel data input is fixed at 0110 (D3=0, D2=1, D1=1, D0=0), and both serial shift inputs (SER_R and SER_L) are permanently fixed at 0.
Trace the output signals Q3, Q2, Q1, and Q0 across all 12 time steps to demonstrate the exact cycle-by-cycle effects of loading, shifting right, and switching direction to shift left.
Constraints
- The shift register is strictly positive-edge triggered.
- A right shift (
DIR=1) moves data fromQ3towardQ0. - A left shift (
DIR=0) moves data fromQ0towardQ3. - Because
SER_RandSER_Lare tied to 0, a0is always shifted into the vacated bit position.
Topics
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