Universal Shift Register
High-speed data communication links and parallel-to-serial converters rely on bidirectional data shifting with parallel loading capabilities. The universal shift register provides complete control over data movement: retaining state, shifting right, shifting left, or loading a full word synchronously.
Implement a 4-bit universal shift register. The 2-bit mode control inputs S1 and S0 dictate the operation performed on the positive clock edge. During a right shift, SER_R enters the most significant bit Q3. During a left shift, SER_L enters the least significant bit Q0.
| S1 | S0 | Operation | Next Q3 | Next Q2 | Next Q1 | Next Q0 | |------|------|-----------|-----------|-----------|-----------|-----------| | 0 | 0 | Hold | Q3 | Q2 | Q1 | Q0 | | 0 | 1 | Shift Right| SER_R | Q3 | Q2 | Q1 | | 1 | 0 | Shift Left | Q2 | Q1 | Q0 | SER_L | | 1 | 1 | Load | D3 | D2 | D1 | D0 |
Constraints
- Use standard D flip-flops for state storage.
- Implement the routing logic using 4:1 multiplexers before each flip-flop.
- All state updates must occur synchronously on the rising edge of the clock.
- Do not use built-in shift register macro blocks.
Topics
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