Universal SR: Mode Transition Sequence Waveform
A 4-bit universal shift register updates its output Q[3:0] on every LOW-to-HIGH transition of CLK based on the control bits MODE1 and MODE0.
The operating modes are: 11 for Parallel Load (D[3:0] into Q[3:0]), 01 for Shift Right (SER_R shifts into Q3), 10 for Shift Left (SER_L shifts into Q0), and 00 for Hold. Nine input signals are provided: CLK (clock, period 2), MODE1 and MODE0 (control bits), D3 through D0 (parallel data), SER_R (serial right input), and SER_L (serial left input). Q[3:0] is initially 0000.
Trace the four output signals Q3, Q2, Q1, and Q0 across all 8 time steps.
Constraints
- Shift Right moves
Q[n]toQ[n-1]and loadsSER_RintoQ3. - Shift Left moves
Q[n]toQ[n+1]and loadsSER_LintoQ0.
Topics
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