Bidirectional SR: Inverted DIR Signal Debug
A bidirectional shift register moves data left or right based on a direction control signal, allowing for flexible serial-to-parallel conversion and data manipulation.
Expected behavior:
When LOAD = 1, the register loads inputs D3, D2, D1, D0 to outputs Q3, Q2, Q1, Q0 on the next clock edge. When LOAD = 0 and EN = 0, the register holds its current value. When LOAD = 0, EN = 1, and DIR = 1 (Left Shift), data shifts towards the most significant bit: Q3 = Q2, Q2 = Q1, Q1 = Q0, and Q0 = LIN. When LOAD = 0, EN = 1, and DIR = 0 (Right Shift), data shifts towards the least significant bit: Q0 = Q1, Q1 = Q2, Q2 = Q3, and Q3 = RIN.
Simulation shows that when LOAD = 0, EN = 1, and DIR = 1 is applied to a register holding 0100 (Q3=0, Q2=1, Q1=0, Q0=0), the next state becomes 0010 instead of the expected 1000. The value shifts right instead of left. The HOLD and LOAD operations function correctly.
Inspect the circuit and correct the fault.
Constraints
- Do not replace or modify the flip-flops.
- You may only add, remove, or modify logic gates on the control signal paths.
- Maintain the existing functionality for
LOADandHOLDstates.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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