Bidirectional SR: PISO Application (Choose Bit Order)
Serial peripheral interface (SPI) controllers must often communicate with devices that expect data either least-significant bit (LSB) first or most-significant bit (MSB) first. A bidirectional parallel-in serial-out (PISO) shift register handles both formats dynamically by changing the shift direction and routing the appropriate end of the register to the output pin.
Construct a 4-bit bidirectional PISO shift register with internal flip-flop states Q3, Q2, Q1, and Q0.
| load | dir | Action | sout | |--------|-------|--------|--------| | 1 | 0 | Parallel load D3, D2, D1, D0 into Q3, Q2, Q1, Q0 | Q0 | | 1 | 1 | Parallel load D3, D2, D1, D0 into Q3, Q2, Q1, Q0 | Q3 | | 0 | 0 | Shift right: Q[2:0] gets Q[3:1], Q3 gets 0 | Q0 | | 0 | 1 | Shift left: Q[3:1] gets Q[2:0], Q0 gets 0 | Q3 |
Constraints
- Use only standard D flip-flops and combinational logic gates.
- Do not use high-level shift register primitives.
- The serial output
soutmust reflect the currently selected end of the register immediately whendirchanges. - Shift in 0 for the empty bit positions during shift operations.
Topics
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