Bidirectional SR: Ping-Pong Data Pattern
A 4-bit bidirectional shift register shifts its bits right (Q3 to Q0) when DIR is 1 and left (Q0 to Q3) when DIR is 0 on every LOW-to-HIGH transition of CLK.
Three input signals are shown: CLK (clock, period 2), DIR (direction control), and SER_IN (serial input for both shift directions). The register outputs are Q3, Q2, Q1, and Q0, initialized to 1, 0, 0, and 0 respectively.
Trace outputs Q3, Q2, Q1, and Q0 across all 16 time steps.
Constraints
- Outputs update only on the LOW-to-HIGH transition of
CLK. - The serial input
SER_INfeedsQ3during a right shift andQ0during a left shift. - Changes to the
DIRsignal between clock edges do not affect the output until the next rising clock edge.
Topics
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