Bidirectional SR: Timing for Direction Change at Terminal Stage
A 4-bit bidirectional shift register shifts its contents right (Q3 towards Q0) when DIR is 1 and left (Q0 towards Q3) when DIR is 0 at every LOW-to-HIGH transition of CLK. The waveform shows four input signals: CLK (clock, period 2), DIR (direction control), SR (right-shift serial input feeding Q3), and SL (left-shift serial input feeding Q0). The register state is represented by outputs Q3, Q2, Q1, and Q0, all initially 0. Trace all four output signals across all 16 time steps.
Constraints
- Outputs only change state on the LOW-to-HIGH transition of
CLK. - The
DIRsignal evaluated precisely at the rising clock edge determines the shift direction for that cycle. - A bit shifted out of the terminal stage in the direction of movement is lost.
Topics
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