Bidirectional SR: Asymmetric Shift Speed Application
Asymmetric serial communication protocols often require hardware that can transmit and receive data at entirely different baud rates.
The circuit provided is an 8-bit bidirectional shift register driven by a master clock CLK running at 100 MHz. Shift direction and timing are controlled by two independent enable signals: EN_R for right-shifting and EN_L for left-shifting. A clock divider circuit generates these enables such that EN_R asserts high every clock cycle, while EN_L asserts high every two clock cycles. The register shifts right when EN_R is high and left when EN_L is high. Data enters serially via D_IN and exits via Q_OUT.
Determine the effective data rates in each direction. Analyze the timing relationship between the shift enables and map this architecture to its intended application.
Constraints
- Master clock
CLKfrequency is exactly 100 MHz. EN_RandEN_Lare mutually exclusive during normal protocol operation.- Setup and hold times of the flip-flops are negligible for these calculations.
Topics
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