Ring Counter
State machines and multi-phase clock generators often require a single active pulse that circulates continuously. The ring counter provides this precise timing sequence by operating a shift register in a closed feedback loop.
Construct a 4-bit ring counter using D flip-flops. When init is 1, the circuit must synchronously load the initial state 1000 on the rising edge of clk. When init is 0, the register shifts its contents on every rising clock edge. The shift path must follow Q3 to Q0, Q0 to Q1, Q1 to Q2, and Q2 to Q3.
| init | clk | Q3 | Q2 | Q1 | Q0 | |--------|-------|------|------|------|------| | 1 | ↑ | 1 | 0 | 0 | 0 | | 0 | ↑ | 0 | 0 | 0 | 1 | | 0 | ↑ | 0 | 0 | 1 | 0 | | 0 | ↑ | 0 | 1 | 0 | 0 | | 0 | ↑ | 1 | 0 | 0 | 0 |
Constraints
- Use exactly four D flip-flops.
- Implement the synchronous initialization logic using multiplexers on the flip-flop data inputs.
- Do not use pre-packaged counter or shift register modules.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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