Ring Counter vs. Johnson Counter: Area Comparison for 8 Phases
Multiphase clock generators in high-speed digital systems often rely on shift register counters to produce non-overlapping control signals. An ASIC requires an 8-phase output sequence to drive a time-interleaved data converter.
Two architectures are proposed: an 8-bit ring counter and a 4-bit Johnson counter. The ring counter uses 8 D-type flip-flops (DFF) connected in a loop with a single circulating active bit. The Johnson counter uses 4 DFF components with inverted feedback from the final stage. Standard cell area estimates dictate that one DFF occupies 6 gate equivalents (GE) and a two-input AND gate (AND2) occupies 1 GE.
Calculate the total area in gate equivalents for each architecture, accounting for any necessary decode logic. Determine the optimal choice for minimizing silicon area and analyze the timing tradeoffs.
Constraints
- A
DFFstandard cell occupies exactly 6 GE. - An
AND2standard cell occupies exactly 1 GE. - The ring counter is assumed to have external initialization to a one-hot state.
- The Johnson counter requires combinatorial decode logic to generate the 8 distinct non-overlapping phases.
Topics
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